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AIC3843
Current-Mode PWM Controller
n FEATURES
l Low Start-Up Current (300A Typical) l Internal Precision Reference. l 500KHz Current-Mode Operation. l Pulse-by-Pulse Current Limiting. l Automatic Feed-Forward Compensation. l Optimized for Off-line and DC/DC Converters. l Under-voltage Lockout with Hysteresis. l Double Pulse Suppression. l High Current Totem Pole Output.
n DESCRIPTION
The AIC3843 control IC provides the features that are necessary to implement off-line or DC/DC Converter fixed-frequency current-mode schemes with a minimum number of external components. This integrated circuits features an under-voltage lockout (UVLO) with approximately 300A start-up current, a precision reference trimmed for accuracy at the error amplifier input, high gain error amplifier, current sensing comparator, logic to insure latched operation, and a totem-pole output stage designed to source or sink high peak current. The output stage, suitable for driving the Nchannel MOSFETs, is low in the off state.
n APPLICATIONS
l AC/DC Off-line Converter. l DC/DC Off-line Converter.
n TYPICAL APPLICATION CIRCUIT
2 C2 R3 51K FEEDBACK SIGNAL 300pF C3 1000P 6 OUTPUT GND 5 VFB 7 VCC + R1 10 R2 20K R5 C6 300P 390 C7 1nF RS 0.33 C1 47F VCC INDUCTOR M1
1 8
COMP VREF
R4 7.5K C5 0.1F
4
RT/CT
ISENSE
3
AIC3843 C4 2.2nF
Current Mode PWM Control Circuit
Analog Integrations Corporation
4F, 9 Industry E. 9th Rd, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5772500 FAX: 886-3-5772510 www.analog.com.tw
DS-3843-00 012102
1
AIC3843
n ORDERING INFORMATION
AIC3843CXXX PACKING TYPE TR: TAPE & REEL TB: TUBE PACKAGE TYPE N: PLASTIC DIP S: SMALL OUT LINE Example: AIC3843CSTR a in SO-8 Package & Taping & Reel Packing Type (CN is not available in TR packing type.)
DIP-8 SO-8 TOP VIEW
COMP 1 VFB 2 ISENSE 3 RT/CT 4 8 VREF 7 VCC 6 OUTPUT 5 GND
PIN CONFIGURATION
n ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Low Impedance Source ) ... ............. ... ... ... ................ ... ... ... ... ... ........................ 30V Supply Voltage (ICC <30mA) ...................... ..... ... ... ... .... ... ... ..... ... ................... ... ... .......... Self Limiting Output Current ................. ... ... ... ... ... ... ... ... ....... ... ... ... ....................... ... ... .... ... ... ............ ......... 1A Output Energy (Capacitive Load) ...................... ........... ... ... ... ... .... ............ ... ... .... ...................... 5J Analog Inputs (Pins 2, 3) ... ........ ... ... ... ... ... ... ... ...... ......... ... ... ... .................... ... ... .... -0.3V to +6.3V Error Amp Output Sink Current ......... ....... .... ... ...... ... ... ... ................... ... ... .... ... ... ... ............... 10mA Operation Temperature Range ......... ....... .... ... ...... ... ... ... .................... ... ... ... ............... -40C~85C ......... ... ... ... ... ... ... ... ... ....... ... ... ... ..... ... ............... 1W ............ ... .... ..... ........ ... ... ... ... ... ... ............. 725mW -65C to +150C SOIC Package Storage Temperature Range Note 1: Power Dissipation at TA 25C DIP Package
........ ... ...... ... ... ... .............................. ... ......... ... ... ...
Lead Temperature (Soldering, 10 seconds) ........ ... ...... ... ... ... ..... ... ... ... ... .... ... ....... ... ........... 300C All voltages are with respect to Pin 5. All currents are positive into the specified terminal.
n TEST CIRCUIT
VREF RT R5 4.7K Q2 2N2222 COMP Error Amp. Adjust R7 4.7K R4 100K VFB R6 10K ISENSE Adjust R3 5K ISENSE RT/CT AIC3843 GROUND CT VCC OUTPUT VREF C2 0.1F R1 1K 1W C1 0.1F A S1 VCC
OUTPUT
GND
2
AIC3843
n ELECTRICAL CHARACTERISTICS {V
otherwise specified.} PARAMETERS CONDITIONS
CC
= 15V (see Note 2), -40C O TA O85C, unless MIN. TYP. MAX. UNITS
Reference Section
Output Voltage Line Regulation Load Regulation Temperature Coefficient of Output Voltage Output Noise Voltage Output Voltage Long Term Drift Short Circuit Output Current Oscillator Section Oscillator Frequency (see Note 3) Frequency Change with Supply Voltage Frequency Change with Temperature Peak-to-Peak Amplitude at RT/CT Error Amplifier Section Feedback Input Voltage Input Bias Current Open-Loop Voltage Amplification Gain-Bandwidth Product Supply Voltage Rejection Ratio Output Sink Current Output Source Current High-Level Output Voltage Low-Level Output Voltage VCC =12V to 25V VFB at 2.7V, COMP at 1.1V VFB at 2.3V, COMP at 5V VFB at 2.3V, RL=15K to GND VFB at 2.7V, RL=15 to VREF VO=2V to 4V 65 0.7 60 2 -0.5 5 COMP at 2.5V 2.42 2.50 -0.3 90 1 70 10 -1 6.2 0.8 1.1 2.58 -2 V A dB MHz dB mA mA V V VCC=12V to 25V 47 52 0.2 57 1 KHz % f =10Hz to 10KHz After 1000H at TA=25C -30 IO=1mA VCC=12V to 25V IO=1mA to 20mA 4.9 5 5 5 0.2 50 5 -85 25 -180 5.1 20 25 0.4 V mV mV mV/C V mV mA
TA=TLOW to THIGH
5 1.7
% V
3
AIC3843
n ELECTRICAL CHARACTERISTICS (Continued)
PARAMETERS Current Sense Section Voltage Amplification Current Sense Comparator Threshold Supply Voltage Rejection Ratio Input Bias Current Delay Time to Output Output Section High-Level Output Voltage ISOURCE=20mA ISOURCE =200mA Low-Level Output Voltage Rise Time Fall Time Under voltage Lockout Section Start Threshold Voltage Minimum Operating Voltage after Start-Up Pulse-Width-Modulator Section Maximum Duty Cycle Minimum Duty Cycle Supply Voltage Start-Up Current Operating Supply Current Limiting Voltage VFB and ISENSE at 0V ICC =25mA 30 0.3 12 34 0.5 17 mA mA V 95 96 100 0 % % 7.8 7.0 8.4 7.6 9.0 8.2 V V ISINK=20mA ISINK=200mA CL=1nF CL=1nF 13 12 13.5 13.4 0.1 1.5 50 50 0.4 2.2 150 150 V V V V nS nS See Note 3 and 4 COMP at 5V, See Note 3 2.85 0.9 3 1 3.15 1.1 V/V V CONDITIONS MIN. TYP. MAX. UNITS
VCC =12V to 25V, See Note 3
70 -2 150 -10 300
dB A nS
Note: 2: Adjust VCC above the start threshold before setting it to 15V. 3. These parameters are measured at the trip point of the latch with VFB at 0V. 4. Voltage amplification is measured between ISENSE and COMP with the input changing from 0V to 0.8V.
4
AIC3843
Error AMP Configuration
2.50V 0.5mA
+ VFB ZI ZF 2 COMP 1
-
Error Amp can Source or Sink up to 0.5mA
Fig. 1
Under-Voltage Lockout
ICC
7
17mA AIC3843 V ON VOFF 8.4V 7.6V 500A V CC
Fig. 2-1 Fig. 2-2 V OFF V ON During under-voltage lockout, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents.
Current Sense Circuit
Error AMP 2R R IS COMP
R RS
1V Current Sense Comparator
C
Current Sense GND Peak Current (Is) is Determined By The Formula I SMAX 1.0V RS
A small RC filter may be required to suppress switch transients.
Fig. 3
5
AIC3843
Oscillator Section
30 100
V REF
8 RT
10 30
CT=100nF
RT (K)
RT/CT GND
4 5 CT
td ( s)
47nF 22nF
10
3 0
10nF 4.7nF 2.2nF 1.0nF
1
For RT>5k, f RT * C T
1.72
0.3
3 1 10 100 10
2 10 3
10
4
10
5
10
6
CT (nF)
Deadtime vs CT (RT>5K )
Frequency (Hz)
Timing Resistance vs. Frequency
Fig. 4-1
7
Fig. 4-2
Fig. 4-3
80
6
Saturation Voltage - (V)
Voltage Gain (dB)
5
-50 40 -100 20 -150 0 -200 -20
3 2 1 0 0.01 SOURCE SAT (Vcc-VoH) SINK SAT (Vol) 0.1 1
10
100
1k
10k
100k
1M
Output Current, Source or Sink - (A)
Frequency (Hz)
Fig. 4-4 Output saturation characteristics
Fig. 4-5 Error Am plifier Open-Loop Frequency Response
Open-Loop Laboratory Fixture
VREF
R1 2N2222 4.7K 1 100K 1K ERROR AMP ADJUST 4.7K 2 V FB COMP AIC3843 8 VREF 7 VCC 0.1F 3 I SENSE OUTPUT 6 0.1F 1k 1W OUTPUT A VCC
5K I SENSE ADJUST
4
R T/C T
GND
5
GND CT
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Fig. 5
Phase (degree)
Vcc=15V TA=+25 solid line TA=-55 dash line
0 60
6
AIC3843
Open-Loop Laboratory Fixture
1k 8 V REF SHUTDOWN 1 COMP
330O
3 I SENSE 500
SHUTDOWN
TO CURRENT SENSE RESISTOR
Fig. 6-1
Fig. 6-2
Shutdown of the AIC3843 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two-diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR, which will be reset by cycling Vcc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
Offline Flyback Regulator
R1 5 1W 117 VAC L1 D6 VARO VM68 C1 250 F 250V 10H
R12
R2 56K 2W 2W 4.7K D4 1N3613 1N3612
C9 3300pF Np
T1
USD945 N5 C10 4700F 10V C11 4700F 10V
+ 5V
COM D7 UFS1002 +12V N12 16V
600V
R4 4.7k
R3 20k 7 2 R5 150k 1 AIC3843 C14 100pF 8 45 6 3 C2
D2 100 F C3 25V 22F R9 68 3W
1N3613 D4
C12
2200 F 12V COM C13
C4 25V 47 F
Nc N12 D8 2200F 16V UES1002
-12V
R7 22 R8 R13 10K
Q1 UFN833 R10 0.55 1W
16V
C5 0.01 F
R6 10k C6
C8 680pF R11 2.7k 2W
0.0022 F USD1120
1k C7 470pF
D5 1N3613
Power Supply Specifications
1. Input Voltage 2. Line Isolation 95VAC to 130VA (50Hz/60Hz) 3750V 5. Output Voltage: A. +5V, 5%; 1A to 4A load Ripple voltage: 50mV P-P Max B. +12V, 3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max C. -12V, 3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max
3. Switching Frequency 40kHz 4. Efficiency @ Full Load 70%
Fig. 7
7
AIC3843
Slope compensation
8
VREF
4
0.1F
RT CT R1 A fraction of the oscillator ramp can be resistively summed with the current sense signal to proved slope compensation for converters requiring duty cycles over 50% Note that capacitor, C forms a filter with R2 to suppress the leading edge switch spikes.
RT/ CT
3
ISENSE AIC3843 C
R2
ISENSE
RSENSE Fig. 8
n BLOCK DIAGRAM
VCC 7 ZD 34V UVLO S/R 5V REF Internal Bias 2.50V 4 RT/CT OSC Error Amp. + D1 D2 VREF Good Logic T S R 2R R Z1 1V Current Sense comparator PWM Latch Q2 8 VREF 5V/50mA
5 GND
Q1 6 OUTPUT
VFB COMP
2 1
3 ISENSE
8
AIC3843
n PIN DESCRIPTIONS
PIN 1: COMP - This pin is the error amplifier output and is made available for loop compensation. PIN 2: VFB - This is the inverting input of the error amplifier. connected It to is the PIN 7: VCC normally PIN 5: GND - This pin is the combined control circuitry and power ground. PIN 6: OUTPUT- This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. - This pin is the positive supply of the control IC. to PIN 8: VREF - This is the reference output. It provides charging current for capacitor CT through resistor RT.
switching power supply output through a resistor divider. PIN 3: ISENSE - A voltage proportional
inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. PIN 4: RT/CT - The oscillator frequency and maximum output duty cycle are programmed by connecting resistor RT to VREF and capacitor C T to ground. It is feasible to operate when f O 500KHz.
n APPLICATION INFORMATIONS
Under voltage Lockout
There are two separate under voltage lockout comparators incorporated to make sure that the IC is fully functional before the output stage is enabled. One is for power supply voltage (VCC) and the other is for reference output voltage (VREF). Each has a built in hysteresis to prevent erratic output behavior when their respective thresholds are crossed. For VCC comparator the upper and lower thresholds are 8.4V and 7.6V, respectively. The large hysteresis and low start up current (0.3mA) of the AIC3843 make it ideally suited in off-line converter applications where The 5.0V reference output is trimmed to 2.0% tolerance at T =25C. It supplies charging current A to the oscillator timing capacitor and is capable of providing current in excess of 20mA for powering additional control system circuitry. In case of overload, the reference is short-circuit protected at efficient bootstrap startup techniques are required. A 34V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system start-up.
Reference Output
9
AIC3843
about 85mA.
oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output (pin 1). The AIC3843 is operated at a current mode since the inductor current is monitored cycle-by-cycle and decides the duty cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the source of output switch M1. This voltage is monitored by the current sense
Error Amplifier
A fully compensated error amplifier is provided with inverting input and output externally accessible. The non-inverting input is internally biased at 2.5V. The converter output voltage is usually divided down and connected to the inverting input. The output of the error amplifier is accessible for external loop compensation, with an offset at two diode drops (1.4V) and divided by three, before connected to the inverting input of the current sense comparator. This guarantees that no drive pulse appears at the output (pin 6).
input (pin 3) and is compared to a level derived from the error amplifier output. In the normal operating conditions the peak inductor current is controlled by the voltage at pin 1 where
IPK = V ( pin 1)- 1. 4V 3RS
Oscillator
The oscillator frequency can be programmed through the setting of timing components RT and CT. Capacitor CT is charged from the 5.0V reference output through R to about 2.8V and T discharged to about 1.2V by the internal discharge current. When CT is discharged the output (pin 6) must be in the low state, thus producing a controlled amount of output
PWM Latch is used to ensure that only a single pulse appears at the output during any given oscillator cycle. However, a narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is tightly loaded.
Output Switch
The AIC3843 contains a single totem-pole output stage that was specifically designed for direct drive of power MOSFET. If any under voltage lockout is detected, internal circuitry will keep the output switch in a sinking current mode, no external pull down resistor is needed.
deadtime. Note that many values of R and C T T can produce the same frequency but only one combination will yield a specific output deadtime at a given frequency.
Current Sense Comparator and PWM Latch
The output switch of AIC3843 is initiated by the
10
AIC3843
n PHYSICAL DIMENSIONS
l 8 LEAD PLASTIC SO (unit: mm)
D
SYMBOL A A1
H E
MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40
MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 1.27
B C D E e
e A C A1
1.27(TYP)
H L
L
B
l
8 LEAD PLASTIC DIP (unit: mm)
D
SYMBOL A1
E1
MIN 0.381 2.92 0.35 0.20 9.01 7.62 6.09 -- 2.92
MAX -- 4.96 0.56 0.36 10.16 8.26 7.12 10.92 3.81
A2 b C
E
D E E1
C
A2 A1
L
e
eB
2.54 (TYP)
b
e
eB L
11

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